Semiconductor devices comprise arrays of memory cells, which are arranged in rows and columns. The memory cells in the same row are switched on and off by word lines. The memory cells in a same column share a pair of bit lines. After the word line fires, the complementary bit lines develop small differential voltage during the read operation. For high-density memory design, small cell size is preferred and usually hundreds of cells are coupled to the same bit lines. Only one cell per bit line is turned on to provide discharging current. This slow discharging process is the main speed limitation for memory read operation. Conventional static sense amplifiers amplify whatever signals are transferred from the bit lines. The time required for the output voltage to reach rail-to-rail voltage level depends on the gain of the sense amplifier and output loading.
FIG. 1 illustrates a circuit diagram of a conventional sense amplifier 101. The sense amplifier 101 includes two positive channel metal oxide semiconductor (PMOS) devices P1 and P2. The PMOS transistors P1 and P2 each have a source coupled to the voltage Vdd and a drain coupled to one of the complementary output nodes, OUT and OUTB. The drain of the PMOS transistor P1 is coupled to the output node OUTB. The drain of the PMOS transistor P2 is coupled to the output node OUT. The PMOS transistors P1 and P2 each have a gate coupled to each other and to ground. The PMOS transistors P1 and P2 each behave like a load device. The inputs of the sense amplifier 101 are coupled to the gate of two negative channel metal oxide semiconductor (NMOS) devices N1 and N2. The gate of the NMOS transistor N1 is coupled to receive the input signal IN. The gate of the NMOS transistor N2 is coupled to receive the input signal INB. The drains of the input transistors N1 and N2 are coupled to the drains of the PMOS transistors P1 and P2, respectively, forming the output nodes OUTB and OUT. The sources of the NMOS transistors N1 and N2 are coupled to each other and to ground through a current source CS.
When the voltage level of the input signal IN is higher than the voltage of the input signal INB, the current I1 flowing through the drains of the transistors P1 and N1 will be higher than the current I2 flowing through the drains of the transistors P2 and N2. The PMOS transistors P1 and P2 are of the same size and under the same gate bias. Accordingly, the PMOS transistors P1 and P2 have approximately the same impedance. Accordingly, the voltage level at the output node OUT will be higher than the voltage level at the output node OUTB. This sense amplifier 101 needs to operate at a voltage level Vdd, where the voltage level Vdd must be greater than the PMOS threshold voltage level Vthp plus the NMOS threshold voltage level Vthn, in order for the sense amplifier 101 to function properly. Also, the sense amplifier 101 input will see bigger capacitive loading compared with a dynamic sense.
Unfortunately, a conventional static pre-amplifier consumes an undue amount of direct current (DC) power while the sense amplifier waits for sufficient input splits.